Verilog 時脈產生器

主程式
clock_all.v

以下程式可在Quartus II 利用modelsim後模擬，且可在電路正確執行，但無法在Modelsim裡正確的前模擬，因為沒有初始值時，Modelsim無法進行運算。

2. // Quartus II Verilog Template
3. // Binary up/down counter
4. // Main clock 50MHz.
5. 
   
6. module clock_all(
7. input clk,
8. output  clock_1MHz,
9. output  clock_100kHz,
10. output  clock_10kHz,
11. output  clock_1kHz,
12. output  clock_100Hz,
13. output  clock_10Hz,
14. output  clock_1Hz,
15. output  clock_01Hz
16. );
17. 
    
18. divider_50 clk0( .clk(clk), .clk_div50(clock_1MHz));
19. divider_10 clk1( .clk(clock_1MHz),  .clk_div10(clock_100kHz));
20. divider_10 clk2( .clk(clock_100kHz),  .clk_div10(clock_10kHz));
21. divider_10 clk3( .clk(clock_10kHz),  .clk_div10(clock_1kHz));
22. divider_10 clk4( .clk(clock_1kHz),  .clk_div10(clock_100Hz));
23. divider_10 clk5( .clk(clock_100Hz),  .clk_div10(clock_10Hz));
24. divider_10 clk6( .clk(clock_10Hz),  .clk_div10(clock_1Hz)); 
25. divider_10 clk7( .clk(clock_1Hz),  .clk_div10(clock_01Hz));
26.   
27. endmodule
28. 
    
29. 
    
30. //=========================================
31. 
    
32. module divider_10(
33. input clk, 
34. output reg clk_div10,
35. output reg [3:0] count_10
36. );
37. 
    
38. always @ (posedge clk)
39. begin
40. if (count_10==4)
41. begin
42. count_10 <= 0;
43. clk_div10<=~clk_div10;
44. end
45. else
46. count_10 <= count_10 + 1;
47. end 
48. endmodule
49. 
    
50. 
    
51. //=========================================
52. 
    
53. module divider_50(
54. input clk,
55. output reg clk_div50,
56. output reg [4:0] count_50
57. );
58. 
    
59. 
    
60. always @ (posedge clk)
61. begin
62. if (count_50==24)
63. begin
64. count_50 <= 0;
65. clk_div50<=~clk_div50;
66. end
67. else
68. count_50 <= count_50 + 1;
69. end
70. endmodule

在Quartus II模擬的test bench 如下：

clock_all_tb.v

1. `timescale 1ns/1ns
2. 
   
3. module clock_all_tb;
4. 
   
5. reg clk;
6. wire clock_1MHz;
7. wire clock_100kHz;
8. 
   
9. clock_all u(
10. .clk(clk),
11. .clock_1MHz(clock_1MHz),
12. .clock_100kHz(clock_100kHz)
13. );
14. 
    
15. initial 
16. begin
17.   #0 
18.   clk = 0;
19. end 
20. 
    
21. always 
22. #10 clk = ~clk;
23. 
    
24. endmodule

當直接使用Modelsim作前模擬時，所有的wire或reg宣告都需要有初始值，需要利用reset使訊號歸零。程式改為

clock_all.v

1. // Quartus II Verilog Template
2. // Binary up/down counter
3. // Main clock 50MHz.
4. 
   
5. module clock_all(
6. input clk,
7. input rst,
8. output  clock_1MHz,
9. output  clock_100kHz,
10. output  clock_10kHz,
11. output  clock_1kHz,
12. output  clock_100Hz,
13. output  clock_10Hz,
14. output  clock_1Hz,
15. output  clock_01Hz,
16. output [4:0] count_50
17. );
18. 
    
19. divider_50 clk0( .clk(clk),          .rst(rst), .clk_div50(clock_1MHz), .count_50(count_50));
20. divider_10 clk1( .clk(clock_1MHz),   .rst(rst), .clk_div10(clock_100kHz));
21. divider_10 clk2( .clk(clock_100kHz), .rst(rst), .clk_div10(clock_10kHz));
22. divider_10 clk3( .clk(clock_10kHz),  .rst(rst), .clk_div10(clock_1kHz));
23. divider_10 clk4( .clk(clock_1kHz),   .rst(rst), .clk_div10(clock_100Hz));
24. divider_10 clk5( .clk(clock_100Hz),  .rst(rst), .clk_div10(clock_10Hz));
25. divider_10 clk6( .clk(clock_10Hz),   .rst(rst), .clk_div10(clock_1Hz)); 
26. divider_10 clk7( .clk(clock_1Hz),    .rst(rst), .clk_div10(clock_01Hz));
27. endmodule
28. 
    
29. //=========================================
30. 
    
31. module divider_10(
32. input clk,
33. input rst, 
34. output reg clk_div10,
35. output reg [3:0] count_10
36. );
37. 
    
38. always @ (posedge clk or negedge rst)
39. begin
40. if (!rst)
41. begin
42. count_10 <= 0;
43. clk_div10<= 0;
44. end
45. else if (count_10==4)
46. begin
47. count_10 <= 0;
48. clk_div10<=~clk_div10;
49. end
50. else
51. count_10 <= count_10 + 1;
52. end 
53. endmodule
54. 
    
55. 
    
56. //=========================================
57. module divider_50(
58. input clk,
59. input rst,
60. output reg clk_div50,
61. output reg [4:0] count_50
62. );
63. 
    
64. always @ (posedge clk or negedge rst)
65. begin
66. if (!rst)
67. begin
68. count_50 <= 0;
69. clk_div50<= 0;
70. end
71. else if (count_50==24)
72. begin
73. count_50 <= 0;
74. clk_div50<=~clk_div50;
75. end
76. else
77. count_50 <= count_50 + 1;
78. end
79. endmodule

test bench 的程式檔如下

clock_all_tb.v

1. `timescale 1ns/1ns
2. 
   
3. module clock_all_tb;
4. 
   
5. reg rst;
6. reg clk;
7. wire clock_1MHz;
8. wire clock_100kHz;
9. 
   
10. clock_all u(
11. .clk(clk),
12. .rst(rst),
13. .clock_1MHz(clock_1MHz),
14. .clock_100kHz(clock_100kHz)
15. );
16. 
    
17. initial 
18. begin
19. #0 
20. clk = 0;
21. rst = 0;
22. #30 rst = 1;
23. 
    
24. end 
25. 
    
26. always 
27. #10 clk = ~clk;
28. 
    
29. endmodule 

用此方法產生時脈，第一步係將50MHz直接除頻至1MHz，原則上係使用除偶數的除頻方法。雖然使用到10MHz時脈的機會不大，但以下設計一個除5的模組，以練習奇數的除頻器。

clock_all.v

1. // Quartus II Verilog Template
2. // Binary up/down counter
3. // Main clock 50MHz.
4. 
   
5. module clock_all(
6. input clk,
7. input rst,
8. output  clock_10MHz,
9. output  clock_1MHz, 
10. output  clock_100kHz,
11. output  clock_10kHz,
12. output  clock_1kHz,
13. output  clock_100Hz,
14. output  clock_10Hz,
15. output  clock_1Hz,
16. output  clock_01Hz,
17. output [4:0] count_50
18. );
19. divider_5  clk0( .clk(clk),          .rst(rst), .clk_div5(clock_10MHz));
20. divider_10 clk1( .clk(clock_10MHz),  .rst(rst), .clk_div10(clock_1MHz));
21. divider_10 clk2( .clk(clock_1MHz),   .rst(rst), .clk_div10(clock_100kHz));
22. divider_10 clk3( .clk(clock_100kHz), .rst(rst), .clk_div10(clock_10kHz));
23. divider_10 clk4( .clk(clock_10kHz),  .rst(rst), .clk_div10(clock_1kHz));
24. divider_10 clk5( .clk(clock_1kHz),   .rst(rst), .clk_div10(clock_100Hz));
25. divider_10 clk6( .clk(clock_100Hz),  .rst(rst), .clk_div10(clock_10Hz));
26. divider_10 clk7( .clk(clock_10Hz),   .rst(rst), .clk_div10(clock_1Hz)); 
27. divider_10 clk8( .clk(clock_1Hz),    .rst(rst), .clk_div10(clock_01Hz));
28. endmodule
29. 
    
30. //=========================================
31. 
    
32. module divider_10(
33. input clk,
34. input rst, 
35. output reg clk_div10,
36. output reg [3:0] count_10
37. );
38. 
    
39. always @ (posedge clk or negedge rst)
40. begin
41. if (!rst)
42. begin
43. count_10 <= 0;
44. clk_div10<= 0;
45. end
46. else if (count_10==4)
47. begin
48. count_10 <= 0;
49. clk_div10<=~clk_div10;
50. end
51. else
52. count_10 <= count_10 + 1;
53. end 
54. endmodule
55. 
    
56. //=========================================
57. 
    
58. module divider_5(
59. input clk,
60. input rst, 
61. output  clk_div5
62. );
63. 
    
64. reg   clk_div5p, clk_div5n;
65. reg [2:0] count_5p, count_5n;
66. 
    
67. always @ (posedge clk or negedge rst)
68. begin
69. if (!rst)
70. begin
71. count_5p <= 0;
72. end
73. else if (count_5p==4)
74. begin
75. count_5p <= 0;
76. end
77. else
78. begin
79. count_5p <= count_5p + 1;
80. end
81. end 
82. 
    
83. always @ (posedge clk or negedge rst)
84. begin
85. if (!rst)
86. begin
87. clk_div5p<= 0;
88. end
89. else if (count_5p<=1)
90. begin
91. clk_div5p<=1'b1;
92. end
93. else
94. begin
95. clk_div5p<=1'b0;
96. end
97. end 
98. 
    
99. always @ (posedge clk or negedge rst)
100. begin
101. if (!rst)
102. begin
103. count_5n <= 0;
104. end
105. else if (count_5n==4)
106. begin
107. count_5n <= 0;
108. end
109. else
110. begin
111. count_5n <= count_5n + 1;
112. end
113. end 
114. 
     
115. always @ (negedge clk or negedge rst)
116. begin
117. if (!rst)
118. begin
119. clk_div5n<= 0;
120. end
121. else if (count_5n<=1)
122. begin
123. clk_div5n<=1'b1;
124. end
125. else
126. begin
127. clk_div5n<=1'b0;
128. end
129. end 
130. 
     
131. assign clk_div5 = clk_div5p | clk_div5n;
132. 
     
133. endmodule 

測試用的test bench

clock_all_tb.v

1. `timescale 1ns/1ns
2. 
   
3. module clock_all_tb;
4. 
   
5. reg rst;
6. reg clk;
7. wire clock_10MHz;
8. wire clock_1MHz;
9. wire clock_100kHz;
10. 
    
11. clock_all u(
12. .clk(clk),
13. .rst(rst),
14. .clock_10MHz(clock_10MHz),
15. .clock_1MHz(clock_1MHz),
16. .clock_100kHz(clock_100kHz)
17. );
18. 
    
19. initial 
20. begin
21. #0 
22. clk = 0;
23. rst = 0;
24. #100 rst = 1;
25. 
    
26. end 
27. 
    
28. always 
29. #10 clk = ~clk;
30. 
    
31. endmodule 

其中，module divider_5係用來將時脈除5，其工作原理係分別使用輸入時脈clk的正、負邊緣觸發。正邊緣觸發clk_div5p在第0及第1兩個完整週期輸出為高準位，負邊緣觸發clk_div5n在第0.5至第2.5兩個週期間輸出為高準位，最後再取or運算，得到2.5週期的高準位。