流水燈

//=======================================================
//  This code is generated by Terasic System Builder
//=======================================================

module button_game2(

//////////// CLOCK //////////
CLOCK_50,
CLOCK2_50,
CLOCK3_50,

//////////// LED //////////
LEDG,
LEDR,

//////////// KEY //////////
KEY,

//////////// SW //////////
SW,

//////////// SEG7 //////////
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7
);

//=======================================================
//  PARAMETER declarations
//=======================================================


//=======================================================
//  PORT declarations
//=======================================================

//////////// CLOCK //////////
input           CLOCK_50;
input           CLOCK2_50;
input           CLOCK3_50;

//////////// LED //////////
output      [8:0] LEDG;
output     [17:0] LEDR;

//////////// KEY //////////
input      [3:0] KEY;

//////////// SW //////////
input     [17:0] SW;

//////////// SEG7 //////////
output      [6:0] HEX0;
output      [6:0] HEX1;
output      [6:0] HEX2;
output      [6:0] HEX3;
output      [6:0] HEX4;
output      [6:0] HEX5;
output      [6:0] HEX6;
output      [6:0] HEX7;


//=======================================================
//  REG/WIRE declarations
//=======================================================

wire [7:0] score;
wire [7:0] death;
wire [3:0] count_1kHz, count_100Hz, count_10Hz, count_1Hz;
wire clock_1Hz, clock_10Hz, clock_100Hz, clock_1kHz, clock_10kHz;

wire b10, b06, b03, b01;

//=======================================================
//  Structural coding
//=======================================================


clock_all ck( .clk(CLOCK_50), .clock_10kHz(clock_10kHz), .clock_1kHz(clock_1kHz), .clock_100Hz(clock_100Hz), .clock_10Hz(clock_10Hz), .clock_1Hz(clock_1Hz));



// divider_10 div( .clk(~KEY[1]), .reset(~KEY[0]), .clk_div10(LEDR[0]), .count_10(count_1Hz) );
SEG7_LUT_8 seg( .oSEG0(HEX0),.oSEG1(HEX1),.oSEG2(HEX2),.oSEG3(HEX3),
.oSEG4(HEX4),.oSEG5(HEX5),.oSEG6(HEX6),.oSEG7(HEX7),
.iDIG( score) );

//PWM p0( .clk(clock_10kHz),   .duty(100), .pwm(b10));
//PWM p1( .clk(clock_10kHz),   .duty( 75), .pwm(b06));
//PWM p2( .clk(clock_10kHz),   .duty( 50), .pwm(b03));
//PWM p3( .clk(clock_10kHz),   .duty( 25), .pwm(b01));



// assign LEDR[17:0] = { b03, b01, 1'b0,b01, b03, b06, b10, b06, b03, b01, 1'b0, b01, b03, b06, b10, b06, b03, b01};

 LEDR_wave L0( .clk_L(clock_10Hz), .clk_H(clock_10kHz), .LEDR( LEDR), .count(score));


//assign LEDR[17] = clock_1Hz;
//assign LEDR[16] = clock_10Hz;

//shrew us( .clk(clock_1Hz), .reset(~SW[0]), .key(KEY), .show_shrew({LEDG[6], LEDG[4], LEDG[2], LEDG[0]}), .score(score), .death(LEDR) );

endmodule

module LEDR_wave(clk_L, clk_H, LEDR, count);

input clk_L, clk_H;
output  reg [17:0] LEDR;

output reg [2:0] count;

wire b10, b06, b03, b01;


PWM p0( .clk(clk_H),   .duty(100), .pwm(b10));
PWM p1( .clk(clk_H),   .duty( 50), .pwm(b06));
PWM p2( .clk(clk_H),   .duty( 20), .pwm(b03));
PWM p3( .clk(clk_H),   .duty( 05), .pwm(b01));



always@(posedge clk_L ) 
begin
count <= count+1;
end


always @(count)
begin
case(count)

3'h00: LEDR[17:0] = { b10, b06, b03, b01,1'b0,1'b0,1'b0,1'b0, b10, b06, b03, b01,1'b0,1'b0,1'b0,1'b0, b10, b06};
3'h01: LEDR[17:0] = { b06, b03, b01,1'b0,1'b0,1'b0,1'b0, b10, b06, b03, b01,1'b0,1'b0,1'b0,1'b0, b10, b06, b10};
3'h02: LEDR[17:0] = { b03, b01,1'b0,1'b0,1'b0,1'b0, b10, b06, b03, b01,1'b0,1'b0,1'b0,1'b0, b10, b06, b10, b06};
3'h03: LEDR[17:0] = { b01,1'b0,1'b0,1'b0,1'b0, b10, b06, b03, b01,1'b0,1'b0,1'b0,1'b0, b10, b06 ,b10, b06, b03};
3'h04: LEDR[17:0] = {1'b0,1'b0,1'b0,1'b0, b10, b06, b03, b01,1'b0,1'b0,1'b0,1'b0, b10, b06 ,b10, b06, b03, b01};
3'h05: LEDR[17:0] = {1'b0,1'b0,1'b0, b10, b06, b03, b01,1'b0,1'b0,1'b0,1'b0, b10, b06 ,b10, b06, b03, b01,1'b0};
3'h06: LEDR[17:0] = {1'b0,1'b0, b10, b06, b03, b01,1'b0,1'b0,1'b0,1'b0, b10, b06 ,b10, b06, b03, b01,1'b0,1'b0};
3'h07: LEDR[17:0] = {1'b0, b10, b06, b03, b01,1'b0,1'b0,1'b0,1'b0, b10, b06 ,b10, b06, b03, b01,1'b0,1'b0,1'b0};


endcase
end

endmodule